Busses are commonly used in computers and other electronic devices to send any number of signals from a driving point to a number of receiving points. These busses can be created in printed circuit technology or from cables attached from one point to another. Backplane busses use circuit cards that plug in at regular intervals and represent loads along the bus. Cable busses employ cables with uniform electrical parameters that are connected at load devices in a "daisy chain" fashion, such as in a SCSI bus implementation.
The SCSI type of bus is also adaptable for use within backplane architectures. In systems of this type, the cable bus is replaced with a printed circuit board backplane. Intelligent peripheral devices, in the form of daughter boards, are then connected to the backplane connectors. The backplane architecture provides a compact and efficient method for connecting a series of intelligent peripheral devices to a computer system.
To work properly, a bus must maintain certain electrical characteristics. One of these characteristics is a controlled impedance. For an unloaded bus (i.e., a bus with no attached intelligent peripheral devices), the intrinsic impedance (Z.sub.0) can be calculated using the intrinsic impedance per unit length (L.sub.0) and the intrinsic capacitance per unit length (C.sub.0) in the following equation: EQU Z.sub.0 =(L.sub.0 /C.sub.0).sup.1/2
For a loaded bus, the preceding equation must be modified to reflect the effect of the attached load devices. This is most always in the form of added capacitance attributable to the attached load devices. Specifically, for a loaded bus the impedance (Z') (Z') can be calculated by modifying the preceding equation to include the load capacitance per unit length (C.sub.d) resulting in the following equation: EQU Z'=(L.sub.0 /(C.sub.0 +C.sub.d)).sup.1/2
Based on this equation, it may be appreciated that increasing the load capacitance per unit length (C.sub.d) will result in decreasing values for the loaded impedance (Z'). Unfortunately, in backplane architectures, the buses are relatively short with each load device being separated by a relatively short distance. Since each load device adds capacitance to the bus, there is a tendency for backplane architectures to have relatively high values for load capacitance per unit length (C.sub.d). The result is that these architectures may be characterized by low intrinsic low values for impedance (Z'). Low values for impedance (Z') results in slow rise and fall times for signals within the bus. This degrades the performance of the bus, making it more prone to operational errors and electrical noise.
To overcome the degrading effects of decreasing impedance, designers have been faced with a difficult compromise. One possible solution is to increase the length of the bus included in backplane architectures. Typically this is achieved by increasing the effective distance that each signal must travel between adjacent intelligent peripheral devices. Unfortunately, this requires that the size of the backplane be increased or that each signal path be routed in a tortuous pattern between adjacent load devices. The use of a tortuous pattern increases the difficulty of routing the signal paths within the backplane and may require that additional signals layers be added to the backplane. In either case, the cost of the backplane can be increased significantly. Another possible solution is to decrease the clock speed of the bus. Of course, this negatively impacts the performance of the bus, thereby making this solution generally unacceptable.
As a result, there is a need for a low-cost, compact backplane that has acceptable electrical signal impedance characteristics and operates at acceptable clock speeds.